1. Field of the Invention
The invention relates generally to electronic materials processing, and more particularly to a system and method for printing thin film transistor arrays.
2. Related Art
Many modern devices, such as video and computer LCD (liquid crystal display) displays, include large arrays of thin film transistors (TFTs). These TFT arrays are commonly referred to as active matrix backplanes and are used to control the media in a display. As the demand for larger devices rises, the corresponding increase in TFT array sizes and interconnect complexities can render impractical the use of conventional chamber-based semiconductor process techniques (i.e., processes that are performed within a vacuum chamber).
Accordingly, alternative TFT production methods are taking on greater importance. A promising approach involves the printing of transistors using methods such as offset printing or jet printing. The use of such integrated circuit (IC) printing techniques can substantially lower transistor production costs, as well as increase manufacturing flexibility, as the substrate material and environmental limitations associated with chamber-based processing techniques can be eliminated.
For example, FIGS. 1A, 1B, and 1C depict a cross-sectional view of stages in a conventional IC printing operation. In FIG. 1A, a gate 130 formed on a substrate 110 is covered by a dielectric 120. A source contact 140 and a drain contact 150 on dielectric 120 define a channel region 101 above gate 130.
In FIG. 1B, a semiconductor printing fluid 160′ is deposited into channel region 101, onto a surface 120-S of dielectric 120 and on to surfaces 140-S and 150-S of source contact 140 and drain contact 150, respectively. Semiconductor printing fluids are printable fluids that dry to leave a semiconductor material. Thus, printing fluid portion 160′ dries into a semiconductor region 160 that forms the active region for a TFT 100, as shown in FIG. 1C.
Unfortunately, as indicated in FIG. 1C, the semiconductor region 160 in conventional printed TFT 100 typically exhibits a very “spread out” geometry, in which only a non-uniform layer of semiconductor material remains in channel region 101. These non-uniformities may comprise variations in thickness of, holes in, or discontinuities in the semiconducting layer. This in turn can lead to poor transistor performance or even device failure, if a discontinuity 160-B develops in semiconductor region 160.
This spreading of printing fluid portion 160′ as it dries is due to the fact that dielectric 120 typically has a very different surface energy from source contact 140 and drain contact 150. Source contact 140 and drain contact 150 are typically formed from some type of metal, which makes them inherently wettable (high surface energy). However, to ensure proper crystalline structure within semiconductor region 160 for some printable semiconductors, it is typically required that surface 120-S of dielectric 120 (on which printing fluid portion 160′ is deposited) be nonwettable (low surface energy).
This disparity in surface energies leads to the problematic spread geometry of semiconductor region 160 in FIG. 1C, as the relatively wettable surfaces 140-S and 150-S of contacts 140 and 150, respectively, tend to draw printing fluid portion 160′ away from the relatively nonwettable surface 120-S in channel region 101. Conventional techniques for preventing this spread of semiconductor printing fluid 160′ have typically involved constructing physical barriers at contacts 140 and 150 or by printing a large amount of excess material (i.e., depositing much more semiconductor printing fluid 160′ than is necessary in an attempt to ensure that semiconductor region 160 is continuous in channel region 101). However, these approaches can add a great deal of cost and complexity to the printed transistor manufacturing process, and are therefore generally undesirable solutions.
Accordingly, it is desirable to provide a system and method for printing high-quality transistors that does not require the formation of physical containment structures on the transistors.